1. Field of the Invention
The present invention relates to arithmetic units for the multiplication of binary numbers, and more particularly, to methods and apparatuses for the multiplication of denormalized IEEE double precision binary floating point numbers.
2. Description of the Background Art
There are many logical structures for computing the arithmetic multiplication of binary numbers; such structures are generally known as multiplier trees. The overall task is the generation and summation of a large set of partial product bits, accounting for their binary weights. When used for floating point operations conforming to the IEEE Standard for Binary Floating-Point Arithmetic, (ANSI/IEEE Std. 754-1985, N.Y., The Institute of Electrical and Electronics Engineers, Inc., Aug. 12, 1985), multiplier trees must decode both normalized and denormalized numbers. A "normalized" number has the most significant bit of its fraction field equal to one; a "denormalized number" has the most significant bit of its fraction field equal to zero.
Because normalized numbers are the ordinary case, it is usually not necessary to explicitly specify the most significant bit. The most significant bit is therefore not part of the operand and is called the "hidden bit." The hidden bit is implied to be equal to one for all normalized numbers. Since denormalized numbers have a hidden bit of zero, there must be a way to determine when a number is denormalized without actually using an explicit bit of representation. The IEEE standard indicates a denormalized number by giving it an exponent value of zero, whereas all normalized numbers have exponents greater than zero. The hidden bit can therefore be directly determined by exponent. If the exponent is zero, the hidden bit of the fraction field of the operand is zero, otherwise it is one. Determining the value of the hidden bits is important because they contribute to the generation of partial products that must be summed by the multiplier tree during the multiplication operation.
Traditionally, multiplier trees have operated simultaneously on all of the partial products generated by the multiplication of the input operands. This required checking the exponent of the operands to generate the hidden bits of their fraction fields before generating the partial products to be input into the multiplier tree. This preliminary checking was needed because the hidden bit of each operand must be logically ANDed with each of the fraction field bits of the other operand in order to generate a complete set of partial products to be summed by the multiplier tree. The general structure for a multiply operation therefore has previously required that the logic generating the hidden bits function in series with the partial product generation logic, thereby increasing the total delays necessary to produce the final product. What is needed is an apparatus and a method for detecting whether the input operands are denormalized, and adding the hidden bit partial products to the fraction field partial products without adding any additional delay time to the multiplication of the input operands.